Polysilicon is the most popular and effective material for electrodes to date and has been used to manufacture integrated circuits. This film has high reliability, and, in particular, the electric resistivity of electrodes and the position of the Fermi level thereof can be controlled by selecting a type of impurity which generates carriers and controlling a doping level. Furthermore, since the film can be deposited by CVD, the film can cover a three dimensionally structured body having a microstructure with high step coverage. Therefore, polysilicon has been the most popular and effective material to date for gate electrodes.
Presently, the thickness of gate insulating films become extremely thin in accordance with a reduction of device size, in the case that impurity-doped polysilicon is used as a gate electrode, it is thought that a minute depletion region formed in the electrode or a small amount of impurity that diffuses into a semiconductor channel region through a gate insulating film will become an obstacle to improving device performance. In particular, using polysilicon for activating carriers contained therein requires depositing or annealing at a high temperature and such a process under the high temperature facilitates a diffusion of the impurity.
Furthermore, since a tunnel leakage current flowing through the gate dielectric film increases in accordance with a miniaturization of the thickness of the gate insulating film, introduction of a high-k gate insulating film will be indispensable to the 65 nm-node micro semiconductor devices from the year 2007. Therefore, recently, numerous studies have been conducted to develop a high-k gate insulating film having a higher dielectric constant than silicon oxide. Then it is found that, if polysilicon is deposited on the high-k gate dielectric film and used as a gate electrode, a problem of pinning of the Fermi level occurs and an improvement of device performance is suppressed. To the 65 nm-node micro semiconductor devices from the year 2007, an introduction of a metal gate electrode will be indispensable. Therefore, presently, numerous studies are being conducted to develop the metal gate material as an alternative material to polysilicon, in which gate depletion and the diffusion of impurity into the semiconductor channel region do not occur, and the pinning phenomenon of the Fermi level does not occur at the high-k gate insulating film.
Metal gate electrode materials generally have a resistivity of 1 mΩcm or lower and this resistivity is lower than that of polysilicon having a resistivity of about 1 mΩcm. Furthermore, the materials have an advantage that the gate depletion does not occur. On the other hand, usually, it is difficult to largely change the position of the Fermi level, because the Fermi level is inherent to the material. Regarding the problem of the diffusion of metal atoms into a semiconductor channel region, it will require some manufacturing ingenuities such as; composing a material used for an electrode of an element having a small diffusion coefficient in a gate dielectric film or in a semiconductor channel region, and not performing a high temperature process should not be performed after deposition of a metal gate electrode film. These manufacturing processes should be carefully designed.
Meanwhile, another problem caused by recent size reduction of transistor devices is a short channel effect. In order to suppress the short channel effect, in which a leakage current flows through a substrate, a structure including an additional gate electrode placed at a position facing a channel, as shown in FIGS. 1(b) and 1(c), has been suggested. Such FETs are called double-gate FETs and categorized into three types of FETs as shown in FIG. 1, on the basis of a positional relation in the structure between gate electrodes and a semiconductor channel.
Among the three types, a structure shown in FIG. 1(b) can be manufactured most easily. In order to manufacture such a device, a manufacturing process must include a step of depositing a dielectric layer and an electrode layer on both side faces of a semiconductor standing on a substrate and a step of depositing an interlayer insulating film, a wiring, and the like on the resulting structure. The introduction of these double-gate FETs (double-gate FETs shown in FIG. 1 are usually called finFETs) will be indispensable to 50 nm-node devices from the year 2009. Therefore, it is desirable to establish such a manufacture process of 50 nm device order including steps of depositing a dielectric layer and an electrode layer on both side faces of the semiconductor standing on the substrate and a following step of depositing the interlayer dielectric film, wiring layer, and the like on the resulting structure.
That is, when a device size is 65 nm, manufacturing accuracy of the metal electrode layer is also required to correspond to 65 nm. Since the manufacturing accuracy is generally 4% or less, a required dimensional manufacturing accuracy is about 2.5 nm. Note that, the manufacturing accuracy of the metal electrode layer is usually referred to as accuracy of film thickness, and generally corresponds to accuracy of flatness. In order to manufacture devices on 65 nm scale, an etching process is also required to be performed on the 65 nm scale. Therefore, it is obvious that the metal electrode layer is also required to be etched on the 65 nm scale.
In order to manufacture a nanometer-scale semiconductor device, nanometer-scale homogeneity is also required. It is known that an insulating dielectric film composed of amorphous material is more homogeneous than one composed of polycrystalline material because the amorphous material has no influence associated with crystal grain boundaries thereof (refer to Patent Document 1 described below).
Therefore, for the electrode material, the amorphous material would be superior to the polycrystalline material in homogeneity. The crystal grain boundaries of the electrode material may play a central role in the pinning of the Fermi level and the role as fixed charges in an interface between an electrode and the insulating dielectric film. Furthermore, it is commonly known that the amorphous material can more effectively serve as a barrier layer against diffusion of impurity atoms than the polycrystalline material since crystal grain boundaries are regions into which impurity atoms are easily diffused.
Therefore, when the gate electrode is composed of polycrystalline, impurities may diffuse into the gate electrode through the crystal grain boundaries from materials contacting surfaces of the gate electrode other than the contact surface of the gate dielectric film. The diffused impurity may serve as the center responsible for the pinning of the Fermi level in the interface between the electrode and the insulating dielectric film. On the other hand, when the gate electrode is composed of amorphous material, such a diffusion of the impurity can be suppressed resulting in the prevention of the pinning of the Fermi level and the increase of the fixed charges.    Patent Document 1: Japanese Unexamined patent Application Publication (Translation of PCT Application) No. 2003-533046    Patent Document 2: Japanese Unexamined patent Application Publication No. 2005-150688    Non-Patent Document 1: T. N. Arunagiri et al. Appl. Phys. Lett. 86 (2005) 083104.